Median architecture by accumulative parallel counters

Journal article

Cadenas, O, Megson, G and Sherratt, S (2015). Median architecture by accumulative parallel counters. IEEE Transactions on Circuits and Systems II: Express Briefs. 62 (7), pp. 661-665. https://doi.org/10.1109/TCSII.2015.2415655
AuthorsCadenas, O, Megson, G and Sherratt, S
Abstract

The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.

KeywordsMedian; Pipelined architectures; 0906 Electrical And Electronic Engineering; Electrical & Electronic Engineering
Year2015
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Journal citation62 (7), pp. 661-665
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISSN1549-7747
Digital Object Identifier (DOI)https://doi.org/10.1109/TCSII.2015.2415655
Publication dates
Print23 Mar 2015
Publication process dates
Deposited09 May 2017
Accepted01 Jan 2015
Accepted author manuscript
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APCMedian-TCAS-II13420-Final.pdf
License: CC BY 4.0

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